1. Technical Field
The present disclosure relates to a semiconductor apparatus and, more particularly, to an apparatus that receives data transmitted through a single transmission line by differential signaling using a single reference voltage.
2. Discussion of Related Art
Semiconductor devices send and receive data signals to and from one another in a system and are required to determine whether the received data signals are logic high or logic low. Thus, the semiconductor devices include a receiver or receiving apparatus that receives data signals and determines whether the received data signals are logic high or logic low.
Semiconductor devices can send and receive data signals using differential signaling or single-ended signaling.
FIG. 1 is a waveform of a data signal generated by single-ended signaling. In single-ended signaling, semiconductor devices are connected with a single data transmission line and data signals DATA are transmitted through the single transmission line.
Single-ended signaling reduces the required number of pins of semiconductor devices but is susceptible to common mode noise compared to differential signaling and has half the input data eye W1 compared to differential signaling.
FIG. 2 is a waveform of data signals generated by differential signaling. In differential signaling, semiconductor devices are connected with two data transmission lines and data signals DATA and inversion data signals /DATA are transmitted through the two data transmission lines.
Differential signaling has superior tolerance to common mode noise compared to single-ended signaling and input data eyes W2 are twice as big as in single-ended signaling. Differential signaling, however, increases the required number of pins of semiconductor devices since two signals, that is, DATA and /DATA are transmitted simultaneously.
Generally, it is required to transmit as much data as possible using a minimum number of transmission lines and expand the input data eye at the same time, so as to reduce system manufacturing costs and to improve system performance.
Thus, a receiving method using a dual reference voltage has been suggested. In the receiving method using a dual reference voltage, data signals are transmitted through a single transmission line as in single-ended signaling, and a receiving apparatus receives data signals by differential signaling using a dual reference voltage.
FIG. 3 is a block diagram illustrating a dual reference voltage receiving apparatus 300. Referring to FIG. 3, the dual reference voltage receiving apparatus 300 includes a first input buffer 310, a second input buffer 330, and a phase detector 350.
The first input buffer 310 is synchronized to a clock signal CLK and is enabled or disabled in response to the clock signal CLK. The first input buffer 310 senses and amplifies the voltage difference between a data signal DATA that is input to a positive + input terminal of the first input buffer 310 and a first reference voltage VREFH that is input to a negative − input terminal of the first input buffer 310, and outputs a first selection signal SEL1.
The second input buffer 330 is synchronized to the clock signal CLK and is enabled or disabled in response to the clock signal CLK. The second input buffer 330 senses and amplifies the voltage difference between a second reference voltage VREFL that is input to a positive + input terminal of the second input buffer 330 and the data signal DATA that is input to a negative input terminal − of the second input buffer 330 and outputs a second selection signal SEL2.
The phase detector 350 detects the phase difference between the first selection signal SEL1 and the second selection signal SEL2 and generates an output signal DI that corresponds to the detected phase difference.
Here, the first reference voltage VREFH is higher than the median level of the data signal DATA, and the second reference voltage VREFL is lower than the median level of the data signal DATA. A voltage that is generated inside the semiconductor device or a power supply voltage VDD can be used for the first reference voltage VREFH, and a voltage that is generated inside the semiconductor device or a ground voltage VSS can be used for the second reference voltage VREFL.
The case when a voltage higher than the median level of the data signal DATA is used as the first reference voltage VREFH, and a voltage that is lower than the median level of the data signal DATA is used as the second reference voltage VREFL is explained below.
FIG. 4 is a circuit diagram of the dual reference voltage receiving apparatus 300 of FIG. 3. FIG. 5 is an exemplary waveform of the data signal DATA in the dual reference voltage receiving apparatus 300, and FIG. 6 is another exemplary waveform of the data signal DATA in the dual reference voltage receiving apparatus 300.
Referring to the signal waveforms in FIGS. 5 and 6, the low data portion of the data signal DATA has the largest voltage difference with respect to the first reference voltage VREFH, and the high data signal portion of the data signal DATA has the largest voltage difference with respect to the second reference voltage VREFL. Therefore, the first input buffer 310 is used for detecting the low data portion of the data signal DATA, and the data signal DATA is compared with the first reference voltage VREFH. The second input buffer 330 is used for detecting the high data signal portion of the data signal DATA, and the data signal DATA is compared with the second reference voltage VREFL.
Because the dual reference voltage apparatus 300 uses two reference voltages, that is, the first and second reference voltages VREFH and VREFL, the dual reference voltage receiving apparatus 300 has relatively complex circuitry and is susceptible to noise during high-speed transmission when compared to a receiving apparatus using single-ended or differential signaling.